1. Field of the Invention
The present invention relates to a method and related apparatus for accessing a memory device of a computer system. In particular, the present invention discloses a method and related apparatus for reordering access requests used to access the memory device of a computer system.
2. Description of the Prior Art
Data processing systems are systems that manipulate, process, and store data, and are well known in the art. Personal computer systems and their associated circuitry are such data processing systems. FIG. 1 is a diagram of a prior art computer system 10. The computer system 10 comprises a central processing unit (CPU) 12, a north bridge circuit 14, a south bridge circuit 16, a display controller 18, a memory device 20, an I/O device 22, and a hard-disk drive 24. The CPU 12 is used to control the operation of the computer system 10. The north bridge circuit 14 is used to arbitrate signals transmitted between the CPU 12 and high-speed peripheral devices such as the display controller 18 and the memory device 20. The display controller 18 is used to handle display data, and the memory device 20 is used to process and store data. The south bridge circuit 16 is used to arbitrate signals transmitted between the north bridge circuit 14 and low-speed peripheral devices such as the I/O device 22 and the hard-disk drive 24. The I/O device 22 (a keyboard for example) is used to receive control signals inputted by an end-user. The hard-disk drive 24 usually is a non-volatile memory device, while the memory device 20 usually is a volatile memory device. The memory device 20 may include a dynamic random access memory (DRAM) to store processing programs and data. For example, the programs and data stored on the hard-disk drive 24 are loaded into the memory device 20 so that the CPU 12 is capable of executing the programs more quickly. Then, the data processed by the CPU 12 are stored back to the memory device 20. It is noted that the north bridge circuit 14 has a memory controller 26 for controlling the access of the memory device 20. When a master device such as the CPU 12 or the display controller 18 issues access requests to the memory controller 26, the memory controller 26 accesses the memory device 20 according to the received access requests. With an in-order access scheme, the memory controller 26 responds to the master device according to the order of the received access requests. For example, the display controller 18 outputs read requests RA1, RA2, RA3, RA4, and RA5 in an order to acquire data D1, D2, D3, D4, and D5 stored in the memory device 20 respectively. Even the memory controller 26 executes the read requests RA1, RA2, RA3, RA4, and RA5 out of its original order, the memory controller 26 will still orderly transmit the retrieved data D1, D2, D3, D4, and D5 to the display controller 18.
FIG. 2 is a diagram showing a first prior art data access operation of the memory device 20. For example, the CPU 12 sequentially produces read requests RA1, RA2, RB1, RB2, RA3, RA4, RB3, RB4, RA5, RA6 for acquiring data DA1, DA2, DB1, DB2, DA3, DA4, DB3, DB4, DA5, DA6, which are stored in the memory device 20. It is assumed that data DA1, DA2, DA3, DA4, DA5, DA6 are all stored on page A of the memory, and data DB1, DB2, DB3, DB4 are all stored on page B. As shown in FIG. 2, the memory controller 26 executes the read requests RA1, RA2, RB1, RB2, RA3, RA4, RB3, RB4, RA5, RA6 in its original order. The memory controller 26 executes the read request RA1 to retrieve data DA1. The memory device 20 transmits the acquired data DA1 to the memory controller 26 via a memory bus. The memory controller 26 then transfers the data DA1 to the CPU 12, thereby completing the data retrieval for the read request RA1. Since data DA2 called by the next read request RA2 is also located on the same page A, the memory device 20 adopts a burst mode to access the data DA2. The data DA2 is quickly retrieved, and is transmitted to the memory controller 26 via the memory bus. The memory controller 26 then transfers the data DA2 to the CPU 12 to finish the data delivery for the read request RA2. However, the read request RB1 is expected to retrieve data DB1 that is located on page B which is different from page A. In order to access the desired page B, the memory device 20 needs to precharge the opened page A first before activating the wanted page B. Therefore, the memory controller 26 successively issues a command PreA for precharging the opened page A, and issues a command ActB for activating the wanted page B. After page B is successfully opened, the memory controller 26 is ready to access data stored on page B. Read requests RB1, RB2 are sequentially executed by the memory controller 26 to retrieve corresponding data DB1, DB2. Then, the memory device 20 provides data DB1, DB2 to the memory controller 26 via the memory bus. The memory controller 26 transfers the acquired data DB1, DB2 to the CPU 12, thereby completing the data retrieval for the read requests RB1, RB2. As the next command calls for data retrieval from page A, commands PreB, ActA are successively issued to precharge the opened page B and activate the wanted page A because data DA3 is located on page A. The above-mentioned process is performed for accessing following data DA3, DA4, DB3, DB4, DA5, DA6 by switching back and forth between page A and B. As it is shown, when two adjacent read requests retrieve data located on different pages, the memory device 20 has to spend extra time to switch between pages. Consequently, the precharging operation and the activation operation deteriorate the overall performance of the memory device 20. As shown in FIG. 2, latency L1 of the memory bus is introduced owing to the precharging operation and the activation operation. Similarly, latency L2 of the host bus is also introduced accordingly due to the imposition of L1.
Generally speaking, when a master device such as the CPU 12 accesses the memory device 20, the precharging operation and the activation operation worsens the performance of the overall data access operation. Therefore, a prior art reordering scheme is used to diminish the effect caused by the precharging operation and the activation operation. FIG. 3 is a diagram showing an improved data access operation of the memory device 20. The CPU 12 sequentially generates read requests RA1, RA2, RB1, RB2, RA3, RA4, RB3, RB4, RA5, RA6 for acquiring data DA1, DA2, DB1, DB2, DA3, DA4, DB3, DB4, DA5, DA6 stored in the memory device 20. The memory controller 26 reorders the received read requests RA1, RA2, RB1, RB2, RA3, RA4, RB3, RB4, RA5, RA6 so that the memory controller 26 executes the read requests RA1, RA2, RA3, RA4, RA5, RA6 before it executes RB1, RB2, RB3, RB4, thereby reducing the time spent on switching between two different pages. As shown in FIG. 3, after the read request RA6 is successfully executed, commands, PreA, ActB are issued by the memory controller 26 for precharging page A and activating page B. Only one page switch operation is performed, and only one latency L1 is introduced for the memory bus. However, the memory controller 26 has to transfer the retrieved data to the CPU 12 according to the original order defined by the sequence in which requests are issued. In other words, the memory controller 26 needs to deliver data DA1, DA2, DB1, DB2, DA3, DA4, DB3, DB4, DA5, DA6 to the CPU 12 sequentially. Even if the memory device 20 retrieves data DA1, DA2, DA3, DA4, DA5, DA6 quickly in a burst mode, after delivering DA1 and DA2, the host bus has to wait until the data DB1 has been retrieved by the read request RB1. It is noted that since DA3, DA4, DA5, DA6 have been successfully retrieved and transferred to the memory controller 26, data DA3, DA4 are immediately transmitted to the CPU 12 after data DB2 has been transmitted to CPU 12. As such, only one latency L2 is introduced for the host bus. Comparing with the first data access operation illustrated in FIG. 2, the data access operation illustrated in FIG. 3 needs fewer page switch operations, but with a much greater latency L2 for the host bus. The performance of the memory bus is improved at the cost of the performance of the host bus. If the read request RB1 is delayed significantly due to the reordering of the requests, the latency L2 can seriously deteriorate the overall data access operation. It is thus also hard to benefit from the reordering of the read requests as illustrated in FIG. 3.